Applicant hereby incorporates by reference Japanese Application No. 2001-011858, filed Jan. 19, 2001, in its entirety. Applicant hereby incorporates by reference U.S. patent application Ser. No. 10/050,793, filed on Jan. 18, 2002, in its entirety.
The present invention includes semiconductor devices having a field effect transistor and a bi-polar transistor, and methods for manufacturing the same.
A MOS field effect transistor with an SOI (Silicon-on-Insulator) structure can be driven at a low power consumption and at a higher speed compared to an ordinary MOS field effect transistor.
FIG. 16 schematically shows one example of a MOS field effect transistor with an SOI structure. An embedded oxide film 1100 that is formed from a silicon oxide film is formed on a silicon substrate 2000. A source region 1200 and a drain region 1300 are formed on the embedded oxide film 1100. A body region 1400 is formed on the embedded oxide film 1100 and between the source region 1200 and the drain region 1300. A gate electrode 1500 is formed over the body region 1400 through a gate dielectric layer.
It is noted that the body region 1400 of the MOS field effect transistor is in a floating state. Accordingly, carriers that are generated by an impact ionization phenomenon are stored in the body region 1400. When carriers are stored in the body region 1400, the potential of the body region 1400 changes. A phenomenon that is a so-called substrate floating effect takes place. When the substrate floating effect occurs, a kink phenomenon and a history effect occur in the MOS field effect transistor.